Development of a fully-depleted thin-body FinFET process

The goal of this work is to develop the processes needed for the demonstration of a fully-depleted (FD) thin-body fin field effect transistor (FinFET). Recognized by the 2003 International Technology Roadmap for Semiconductors as an emerging non-classical CMOS technology, FinFETs exhibit high drive current, reduced short-channel effects, an extreme scalability to deep submicron regimes. The approach used in this study will build on previous FinFET research, along with new concepts and technologies. The critical aspects of this research are: (1) thin body creation using spacer etchmasks and oxidation/etchback schemes, (2) use of an oxynitride gate dielectric, (3) silicon crystal orientation effect evaluation, and (4) creation of fully-depleted FinFET devices of submicron gate length on Silicon-on-Insulator (SOI) substrates. The developed process yielded functional FinFETs of both thin body and wide body variety. Electrical tests were employed to describe device behaviour, including their subthreshold characteristics, standard operation, effects of gate misalignment on device performance, and impact of crystal orientation on device drive current. The process is shown to have potential for deep submicron regimes of fin width and gate length, and provides a good foundation for further research of FinFETs and similar technologies at RIT

Study of Nickel Silicide Processes for Advanced CMOS Applications

A study has been performed to determine critical mechanisms involved in formation of nickel suicides. The process parameters under investigation were silicidation temperature, presilicide N2+ implant, and the presence of a titanium capping layer. Contact sheet resistance phosphorous-implanted silicon was measured and determined to degrade with high silicidation temperature. Titanium capping was found to improve contact resistance and compensate for the effects of high temperature treatment for polycides. The nitrogen incorporation via implant shows a degradation in resistivity for both silicides and polycides

Journal of Microelectronic Research - May 2003

https://scholarworks.rit.edu/meec_archive/1012/thumbnail.jp

Diffusion barrier cladding in Si/SiGe resonant interband tunneling diodes and their patterned growth on PMOS source/drain regions

Abstract—Si/SiGe resonant interband tunnel diodes (RITDs) employing-doping spikes that demonstrate negative differential resistance (NDR) at room temperature are presented. Efforts have focused on improving the tunnel diode peak-to-valley current ratio (PVCR) figure-of-merit, as well as addressing issues of manufacturability and CMOS integration. Thin SiGe layers sandwiching the B-doping spike used to suppress B out-diffusion are discussed. A room-temperature PVCR of 3.6 was measured with a peak current density of 0.3 kA/cmP. Results clearly show that by introducing SiGe layers to clad the B-doping layer, B diffusion is suppressed during post-growth annealing, which raises the thermal budget. A higher RTA temperature appears to be more effective in reducing defects and results in a lower valley current and higher PVCR. RITDs grown by selective area molecular beam epitaxy (MBE) have been realized inside of low-temperature oxide openings, with performance comparable with RITDs grown on bulk substrates. Index Terms—CMOS compatibilty, dopant diffusion, Ge-Si alloys, low-temperature oxide, molecular beam epitaxy, negative differential resistance, patterned growth, rapid thermal annealing, resonant interband tunneling diodes, silicon. I